The invention is related to the field of PLL, and in particular to a segmented Fractional-N PLL.
In a traditional Integer-N PLL, if finer output frequency resolution is desired, one approach is to pre-divide the input clock in order to lower the reference clock frequency. Since the output frequency is an integer (N) times the input frequency, a slower reference clock results in a finer frequency resolution. Using this approach, the maximum achievable PLL bandwidth is reduced since the loop bandwidth should not greatly exceed 10% of the reference clock frequency. Lowering the loop bandwidth sacrifices VCO phase noise and increases layout area due to the larger capacitors sizes required in the loop filter. The other approach to achieve finer frequency resolution with an integer-N PLL is to increase the output frequency and then divide down the resulting VCO output clock. This approach has the significant disadvantage of increased power consumption due to the higher clock rate.
A better approach to derive finer output frequency resolution is to use a Fractional-N PLL. With this approach, the feedback divider is typically controlled by a delta-sigma modulator such that the average divider setting achieves the desired (fractional) value. In using a delta-sigma modulator to control the feedback divider, the quantization noise induced by the modulator will be shaped such that it is placed mostly at higher frequencies. The quantization noise can then be attenuated by the PLL's low-pass characteristic as seen at its input. While the Fractional-N approach enables a higher reference clock rate thereby enabling a higher loop bandwidth as set by stability constraints, the filtering constraints imposed by quantization noise may still limit the loop bandwidth to an undesired level.
One efficient method to soften the PLL bandwidth requirement resulting from quantization noise is to reduce the feedback divider step using sub-phase generation. However, if the sub-phase generation circuit (phase interpolator, delay line or other method) has non-idealities (mismatch, gain error and any other effects), the sub-phase generation circuit inevitably introduces spurs into the PLL system. Note these spurs would be in addition to the fractional spurs that can result from native idle tones in the delta-sigma modulator.